ASIC Design Efficiency Engineer
Santa Clara, CA, United States • Posted June 02, 2026
Job Type:
Full-time
Location:
Santa Clara, CA
Posted:
June 02, 2026
Category:
other-general
Application Deadline:
June 07, 2026
Role Description
We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!
What you'll be doing:
+ Develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency.
+ Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
+ Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
+ Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performin...
What you'll be doing:
+ Develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency.
+ Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
+ Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
+ Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performin...
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