ASIC Design Engineer - Staff
vancouver, metro vancouver regional district, Canada • Posted June 27, 2026
Job Type:
Full-time
Location:
vancouver, metro vancouver regional district
Posted:
June 27, 2026
Category:
Engineering
Application Deadline:
August 06, 2026
Role Description
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. The ideal candidate will play a crucial role in designing and developing ASICs for cutting‑edge technologies.
Key Responsibilities:
- Design and implement digital circuits using HDL (Verilog/System Verilog).
- Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis.
- Optimize designs for performance, power, and area (PPA) requirements.
- Perform RTL simulation and verification to ensure design functionality.
- Participate in design reviews and provide technical guidance to team members....
Interested in this role?
Click the button below to start your application for ASIC Design Engineer - Staff at Celero Communications, Inc..
Apply Now