ASIC Engineer
Barcelona, Spain, Spain • Posted June 03, 2026
Job Type:
Full-time
Location:
Barcelona, Spain
Posted:
June 03, 2026
Category:
other-general
Application Deadline:
June 07, 2026
Role Description
**Meet the Team**
Join the Physical Design CAD & Methodology Team—a technically strong group responsible for developing and supporting RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs.
Our team works closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to enable efficient execution, consistent QoR, and reliable tape-outs. We value engineers who combine hands-on technical depth with a growing sense of ownership, collaboration, and continuous improvement. If you enjoy improving flows, solving complex PD problems, and expanding your technical influence, this role is a great fit.
**Your Impact**
As a Physical Design Flow & Methodology Engineer, you will take end-to-end ownership of key portions of the PD flow, contributing to implementation and signoff methodology from synthesis handoff through GDS delivery.
You will develop, enhance, and maintain block- and chip-level PD f...
Join the Physical Design CAD & Methodology Team—a technically strong group responsible for developing and supporting RTL-to-GDS Physical Design implementation and signoff flows across multiple ASIC programs.
Our team works closely with Physical Design, STA, Power, Physical Verification, and Front-End teams to enable efficient execution, consistent QoR, and reliable tape-outs. We value engineers who combine hands-on technical depth with a growing sense of ownership, collaboration, and continuous improvement. If you enjoy improving flows, solving complex PD problems, and expanding your technical influence, this role is a great fit.
**Your Impact**
As a Physical Design Flow & Methodology Engineer, you will take end-to-end ownership of key portions of the PD flow, contributing to implementation and signoff methodology from synthesis handoff through GDS delivery.
You will develop, enhance, and maintain block- and chip-level PD f...
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