Cellular SoC Static Timing Analysis Engineer
Sunnyvale, CA, United States • Posted June 05, 2026
Job Type:
Full-time
Location:
Sunnyvale, CA
Posted:
June 05, 2026
Category:
other-general
Application Deadline:
June 11, 2026
Role Description
**Role Number:** 200628423-3956
**Summary**
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple’s custom silicon. You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you’ll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?
As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.
**Descripti...
**Summary**
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple’s custom silicon. You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you’ll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?
As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.
**Descripti...
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