Clock / Power Hw Validation Engineer
tijuana, tijuana, Mexico • Posted June 05, 2026
Job Type:
Full-time
Location:
tijuana, tijuana
Posted:
June 05, 2026
Category:
Other-General
Application Deadline:
July 15, 2026
Role Description
**Company**:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
**Job Area**:Engineering Group, Engineering Group > ASICS Engineering
**General Summary**:
Roles & Responsibilities:
- Own the E2E bare metal framework validation of Qualcomm mobile/ server/ compute SoC clock and power architectures
- Validation planning - understand design changes, visualize standalone and system level test requirements and scenarios
- Test plan development - clearly document test strategy and dependencies
- Conduct validation strategy and test plan review with all stakeholders - architects, designers, verification engineers, software engineers
- Efficiently collaborate with teams in different time zones - both internal and external
- Automate validation process - development, execution, inference using python, perl, shell
- Develop scalable device drivers, standalone and system tests using C
- Review validation platform schematics to ensure post-Si debug supp...
**Job Area**:Engineering Group, Engineering Group > ASICS Engineering
**General Summary**:
Roles & Responsibilities:
- Own the E2E bare metal framework validation of Qualcomm mobile/ server/ compute SoC clock and power architectures
- Validation planning - understand design changes, visualize standalone and system level test requirements and scenarios
- Test plan development - clearly document test strategy and dependencies
- Conduct validation strategy and test plan review with all stakeholders - architects, designers, verification engineers, software engineers
- Efficiently collaborate with teams in different time zones - both internal and external
- Automate validation process - development, execution, inference using python, perl, shell
- Develop scalable device drivers, standalone and system tests using C
- Review validation platform schematics to ensure post-Si debug supp...
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