CPU Physical Design Engineer
Santa Clara, CA, United States • Posted June 01, 2026
Job Type:
Full-time
Location:
Santa Clara, CA
Posted:
June 01, 2026
Category:
other-general
Application Deadline:
June 08, 2026
Role Description
**Role Number:** 200657366-3760
**Summary**
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design.
**Description**
As a CPU Physical Design Engineer, you will drive or participate in the following:
• Drive RTL-to-GDS design convergence through logic synthesis and place-and-rout...
**Summary**
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design.
**Description**
As a CPU Physical Design Engineer, you will drive or participate in the following:
• Drive RTL-to-GDS design convergence through logic synthesis and place-and-rout...
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