DDR Design Verification Lead -Remote

Prem Nagar, Punjab, India • Posted June 06, 2026

Job Type: Full-time
Location: Prem Nagar, Punjab
Posted: June 06, 2026
Category: Computer Occupations
Application Deadline: July 16, 2026

Role Description

Job Overview We are looking to hire a strong DV engineer to work on verification of LPDDR5/DDR based IPs and Subsystems in the Infra IP team


  • Create DV infrastructure for verification
  • Integrate VIP's
  • Create and execute test plans, debug failures, write assertions, close code and functional coverage
  • Ensure high quality verification
  • Working with all stakeholders to ensure program success


Minimum Qualifications Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.


10+ years Design Verification experience or related work experience.


Preferred Qualifications Following skill set is required:


  • Strong Debug, UVM, System Verilog
  • Understanding Specs and Standards and developing relevant test plans
  • Monitors, scoreboards, sequencers and sequences, that utilize scrip...

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