Design Enablement Engineer II

Shanghai, Shanghai, China • Posted June 15, 2026

Job Type: Full time

Location: Shanghai, Shanghai

Posted: June 15, 2026

Category: Engineers

Application Deadline: July 25, 2026

Role Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key responsibilities
Leverage silicon verification platform and environment to create necessary post-silicon infrastructure, methodology and automation to allow tests executed in a timely and efficient manner.
Integrate silicon, HW, firmware, and system software into a complete system which includes various InfiniBand and PCIe protocols, PXE booting, virtual machines, secure networks, Ethernet and Ethernet-over-InfiniBand, sockets and RPC calls, FPGA, microcontroller interfaces, JTAG, I2C, SPI, SERDES, memory and many other interfaces.
Execute post-silicon tests to expose design issues, validate product against the specifications including performance, and qualify the design for production release.
Review, replicate, and respond to customer issues. Perform initial analysis of error logs from customer design sim...
                

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