Design engineer
Chennai, Tamil Nadu, India • Posted May 27, 2026
Job Type:
Full-time
Location:
Chennai, Tamil Nadu
Posted:
May 27, 2026
Category:
Engineers
Application Deadline:
July 06, 2026
Role Description
ASIC/DFT Engineers
Experience : 3-4 years
location : Chennai
Experience in simulation and silicon validation.
Strong expertise in DFT concepts, pattern simulation, silicon debug, and yield enhancement is required.
Hands-on experience in ATPG (coverage analysis) and memory verification, repair, and failure root-cause analysis is essential.
Experience with tools like Test Kompress (ATPG), Mentor ETVerify (MBIST), and simulation tools such as VCS/Model Sim is preferred.
Scripting knowledge in Perl/Shell is a plus along with adaptability to new tools and methodologies.
Looking for candidates who can thrive in dynamic, global teams and handle multiple high-priority projects.
Apply now: janagaradha.n@
| Notice Period: 0–15 days | Location: Chennai
Experience : 3-4 years
location : Chennai
Experience in simulation and silicon validation.
Strong expertise in DFT concepts, pattern simulation, silicon debug, and yield enhancement is required.
Hands-on experience in ATPG (coverage analysis) and memory verification, repair, and failure root-cause analysis is essential.
Experience with tools like Test Kompress (ATPG), Mentor ETVerify (MBIST), and simulation tools such as VCS/Model Sim is preferred.
Scripting knowledge in Perl/Shell is a plus along with adaptability to new tools and methodologies.
Looking for candidates who can thrive in dynamic, global teams and handle multiple high-priority projects.
Apply now: janagaradha.n@
| Notice Period: 0–15 days | Location: Chennai
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