Design Engineer

We are looking for a SoC DFX DV Lead to drive chip-level DFX verification activities, develop verification strategies, and ensure high-quality execution of SoC DV flows. The role involves DFX test planning, testbench and testcase development, cross-die co-simulation, power-aware verification, and supporting silicon bring-up and ATE testing.

Key Responsibilities

• Lead SoC DFX verification activities and resource planning.
• Develop DFX test plans, testbenches, and verification test cases.
• Drive DFX DV quality reviews and milestone signoffs.
• Support cross-die co-simulation and power-aware simulations.
• Collaborate with test engineering teams for silicon bring-up and ATE testing.
• Improve DFX DV flow robustness and efficiency.

Required Skills & Experience

• Strong Verilog RTL design and verification experience.
• Knowledge of SystemVerilog, UVM, Scan, and BIST is preferred.