Design for Testability Engineer
Bengaluru, Karnataka, India • Posted June 04, 2026
Job Type:
Full-time
Location:
Bengaluru, Karnataka
Posted:
June 04, 2026
Category:
Engineers
Application Deadline:
July 14, 2026
Role Description
Experience: 5 - 7 years as DFT Engineer
Location: Bangalore
Required Skills
- Scan insertion
- SCAN DRC/Coverage debug
- ATPG Pattern generation
- Gate level simulations ( Zero delay/Timing Delay simulations)
- Worked on JTAG/P1500 protocols
- Perl/Tcl scripting
- Timing/Formal verification/PD flow knowledge is plus
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