Design Validation Engineer

SOC RTL Design Verification Experience : 4 to 10 Years Development and verification of post-si validation sequences using C/C++- Experienced with Verilog, System Verilog, and C or C++- Candidate past experience requirements, - Should have experience in system-level Verification.
- DDR prior experience is not mandatory. ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation.