Design Verification Engineer
Mumbai, Maharashtra, India • Posted May 31, 2026
Job Type:
Full-time
Location:
Mumbai, Maharashtra
Posted:
May 31, 2026
Category:
Engineers
Application Deadline:
July 10, 2026
Role Description
Experience: 5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics
Roles and Responsibilities
- Verilog, System verilog, UVM
- VHDL, UVVM
- Simulator exposure with VCS, Questa, Xcelium
- Proficient in simulation and HW languages
- Should be able to interpret various LRMs and comply with semantics and testcase creation.
Share the profiles to [email protected].
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics
Roles and Responsibilities
- Verilog, System verilog, UVM
- VHDL, UVVM
- Simulator exposure with VCS, Questa, Xcelium
- Proficient in simulation and HW languages
- Should be able to interpret various LRMs and comply with semantics and testcase creation.
Share the profiles to [email protected].
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