Design Verification Engineer, Silicon and Systems Group
Bengaluru, India, India • Posted June 03, 2026
Job Type:
Full-time
Location:
Bengaluru, India
Posted:
June 03, 2026
Category:
other-general
Application Deadline:
June 08, 2026
Role Description
Description
As a Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on simulation and emulation platforms.
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
• Architect and implement verification environments for complex functional blocks
• Create and enhance verification environments using SystemVerilog and UVM
• Develop comprehensive test plans through collaboration with design engineers, SW and architects
• Implement...
As a Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on simulation and emulation platforms.
You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will:
• Architect and implement verification environments for complex functional blocks
• Create and enhance verification environments using SystemVerilog and UVM
• Develop comprehensive test plans through collaboration with design engineers, SW and architects
• Implement...
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