Digital IC Verification Engineer
Parma, Emilia-Romagna, Italy • Posted May 30, 2026
Job Type:
Permanent
Location:
Parma, Emilia-Romagna
Posted:
May 30, 2026
Category:
Textile, Apparel, and Furnishings Workers
Application Deadline:
July 09, 2026
Role Description
Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.
Job duties:
Developing test plans, tests and verification infrastructure using SV/UVM methodology Building reusable bus functional models, monitors, checkers and scoreboards Performing coverage driven verification closure Performing block level, multi-block level and system-level verification Performing Gate level simulations Performing Mixed Signal simulations Implementing Regression tests Performing Formal Verification Working closely with IC designers and post-silicon engineers Qualifications and Background
Requirements:
Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation Knowledge/experience in scripting languages, such as Tcl and Python<...
Job duties:
Requirements:
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