Digital verification engineer

Digital Verification Engineer
Experience: 6+ years
Key Responsibilities
- Develop and execute verification plans based on design and architecture specifications.
- Build System Verilog/UVM-based testbenches and reusable verification components.
- Create directed and constrained-random test cases for functional and corner-case verification.
- Debug simulation failures using industry-standard tools and collaborate with RTL designers to resolve issues.
- Define, measure, and close functional and code coverage gaps.
- Implement System Verilog Assertions (SVA) for protocol and behavioral checking.
- Run and monitor regression suites; triage failing tests and track issues.
- Participate in specification reviews, design reviews, and verification progress meetings.
- Maintain clear documentation for testbench architecture, test scenarios, and verification results.
- Automate verification workflows using scripting languages such as Python, Perl, Shell, or Tcl...