Discipline Engineer

Bengaluru, Karnataka, India • Posted June 06, 2026

Job Type: Full-time

Location: Bengaluru, Karnataka

Posted: June 06, 2026

Category: Engineers

Application Deadline: July 16, 2026

Role Description

                    SoC DFT Engineer Job Description: Scan insertion. SCAN DRC/Coverage debug. ATPG Pattern generation. Gate level simulations ( Zero delay/Timing Delay simulations). Worked on JTAG/P1500 protocols. Perl/Tcl scripting. Timing/Formal verification/PD flow knowledge is plus. Location: Bangalore Notice Period: Immediate Experience: 5+ Years
                

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