Engenheiro (a) FPGA - Remoto
eusébio, estado do ceará, Brazil • Posted June 04, 2026
Job Type:
Full-time
Location:
eusébio, estado do ceará
Posted:
June 04, 2026
Category:
Other-General
Application Deadline:
July 14, 2026
Role Description
- Advanced english
- Design, simulate, implement and test digital logic for FPGA using Verilog
- Perform synthesis, timing analysis, floorplanning and test using Xilinx Vivado and Synopsys HAPS tools. Write constraints to fix timing problems.
- Programming skills in TCL (for Vivado and openOCD) and python.
- Experience in board tests using JTAG probes for ARM cores, logic analyzer, serial ports, Vivado's ILA probes, etc.
- Experience in use AI in the daily tasks, tool flow improvement and project analysis.
- Experience in SoC design or verification is a plus.
- Experience in Emulation (HAPS, Zebu, Palladium) is a plus.
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