Fpga design engineer
Bengaluru, Karnataka, India • Posted June 03, 2026
Job Type:
Full-time
Location:
Bengaluru, Karnataka
Posted:
June 03, 2026
Category:
Engineers
Application Deadline:
July 13, 2026
Role Description
ACL Digital is Hiring – FPGA Synthesis Engineers (Automotive) ⚡
Location: Bangalore | ⏳ Notice Period:
Role – Individual Contributor (IC):
• Strong hands-on experience in FPGA Synthesis & Implementation using tools like Vivado/Quartus/Synplify
• Expertise in RTL synthesis, timing closure, constraints (SDC/XDC), and STA
• Experience with FPGA bring-up, gate-level simulations, and debugging timing/functional issues
• Good understanding of ASIC/FPGA flows, CDC/RDC, lint, and low-power considerations
• Exposure to Automotive / Safety (ISO26262) projects is highly preferred
• Ability to work closely with RTL, Verification, and Physical Design teams for end-to-end closure
Interested candidates, please share your profile at
#ACLDigital #Hiring #FPGA #Synthesis #Automotive #Bangalore Jobs #Semiconductor #VLSI #Timing Closure
Location: Bangalore | ⏳ Notice Period:
Role – Individual Contributor (IC):
• Strong hands-on experience in FPGA Synthesis & Implementation using tools like Vivado/Quartus/Synplify
• Expertise in RTL synthesis, timing closure, constraints (SDC/XDC), and STA
• Experience with FPGA bring-up, gate-level simulations, and debugging timing/functional issues
• Good understanding of ASIC/FPGA flows, CDC/RDC, lint, and low-power considerations
• Exposure to Automotive / Safety (ISO26262) projects is highly preferred
• Ability to work closely with RTL, Verification, and Physical Design teams for end-to-end closure
Interested candidates, please share your profile at
#ACLDigital #Hiring #FPGA #Synthesis #Automotive #Bangalore Jobs #Semiconductor #VLSI #Timing Closure
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