Full Chip Front-End DFT Engineer

Bengaluru, India, India • Posted June 01, 2026

Job Type: Full-time
Location: Bengaluru, India
Posted: June 01, 2026
Category: other-general
Application Deadline: June 08, 2026

Role Description

Full Chip Front-End DFT Engineer

_corporate_fare_ Google _place_ Bengaluru, Karnataka, India

**Advanced**

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

**Minimum qualifications:**

+ Bachelor's degree in Science or Electrical or Electronics Engineering or a related technical field or equivalent practical experience.
+ 5 years of experience with ATPG, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow.
+ 3 years of experience with SoC-level DFT architecture, implementation, and validation.
+ Experience with SoC DFT RTL implementation, RTL verification, Automatic Test Pattern Generation (ATPG)/MBIST/Boundary Scan (BSCAN)/Idd Quiescent Current (IDDQ) pattern generation.
+ Experience with DFT Embedded Deterministic Test (EDA) tool Tessent.

**Preferred qualifications:**

+...

Interested in this role?

Click the button below to start your application for Full Chip Front-End DFT Engineer at Google.

Apply Now