Gate-level SigEM/SEB/FIT CAD Engineer

Austin, TX, United States • Posted June 15, 2026

Job Type: Full-time
Location: Austin, TX
Posted: June 15, 2026
Category: other-general
Application Deadline: June 22, 2026

Role Description

**Role Number:** 200647960-0240

**Summary**
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, S...

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