GPU Software Architecture Engineer, Graphics, Games, & ML
Cupertino, CA, United States • Posted June 15, 2026
Job Type:
Full-time
Location:
Cupertino, CA
Posted:
June 15, 2026
Category:
other-general
Application Deadline:
June 20, 2026
Role Description
**Weekly Hours:** 40
**Role Number:** 200628202-0836
**Summary**
Apple Silicon GPU SW architecture team within the Media, Graphics & Compute Technologies group is seeking a senior/principal engineer to lead server-side ML acceleration and multi-node distribution initiatives. You will help define and shape our future GPU compute infrastructure on Private Cloud Compute that enables Apple Intelligence.
**Description**
In this role, you'll be at the forefront of architecting and building our next-generation distributed ML infrastructure, where you'll tackle the complex challenge of orchestrating massive network models across server clusters to power Apple Intelligence at unprecedented scale. It will involve designing sophisticated parallelization strategies that split models across many GPUs, optimizing every layer of the stack—from low-level memory access patterns to high-level distributed algorithms—to achieve maximum hardware utilization while minimizing lat...
**Role Number:** 200628202-0836
**Summary**
Apple Silicon GPU SW architecture team within the Media, Graphics & Compute Technologies group is seeking a senior/principal engineer to lead server-side ML acceleration and multi-node distribution initiatives. You will help define and shape our future GPU compute infrastructure on Private Cloud Compute that enables Apple Intelligence.
**Description**
In this role, you'll be at the forefront of architecting and building our next-generation distributed ML infrastructure, where you'll tackle the complex challenge of orchestrating massive network models across server clusters to power Apple Intelligence at unprecedented scale. It will involve designing sophisticated parallelization strategies that split models across many GPUs, optimizing every layer of the stack—from low-level memory access patterns to high-level distributed algorithms—to achieve maximum hardware utilization while minimizing lat...
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