Memory layout engineer
Bengaluru, Karnataka, India • Posted June 03, 2026
Job Type:
Full-time
Location:
Bengaluru, Karnataka
Posted:
June 03, 2026
Category:
Engineers
Application Deadline:
July 13, 2026
Role Description
ACL Digital is looking for smart and enterprising Memory Layout Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting.
Experience: 4 to 5 Years
Skills :
Having lower node Finfet experience. (10nm & less)
Memory compiler layout, SRAM, Register File (RF)
Available to join in 3-4 weeks.
Location: Noida/ Hyderabad
For more details Contact:
Email:
Experience: 4 to 5 Years
Skills :
Having lower node Finfet experience. (10nm & less)
Memory compiler layout, SRAM, Register File (RF)
Available to join in 3-4 weeks.
Location: Noida/ Hyderabad
For more details Contact:
Email:
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