MSDV Engineer
Galway, Galway, Ireland • Posted June 03, 2026
Job Type:
Part Time
Location:
Galway, Galway
Posted:
June 03, 2026
Category:
Engineers
Application Deadline:
July 13, 2026
Role Description
Mixed Signal Design Verification Engineer Implementation of System Verilog Models for the Analog blocks Model vs Schematic Verification – System Verilog Test bench implementation including assertions Understanding of adding connect module at the interaction of schematic and model while running AMS simulations Understanding of UVM environment and implementing the Top Level Test cases in the environment Running regressions using VManager.
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