Principal Design Engineer (Virtual Solution)

Shanghai, Shanghai, China • Posted June 20, 2026

Job Type: Full time

Location: Shanghai, Shanghai

Posted: June 20, 2026

Category: Engineers

Application Deadline: July 30, 2026

Role Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
Develop end-to-end verification flows including:AVIP integrationTestbench and system modelingBare-metal / driver-level validation
Architect scalable solutions for multi-protocol system validation across multiple clock domains
Optimize solutions for performance, scalability, and emulation efficiency
Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
Contribute to next-generation AVIP method...
                

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