Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout)

We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

• Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
• Collaborate with design engineers to understand design requirements and translate them into precise layouts.
• Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
• Work closely with the physical design team to integrate custom blocks into the overall chip design.
• Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
• Conduct design reviews and provide technical feedback to improve ...