Principal RTL Engineer – FPGA Debug & EDA Architecture

Mumbai, Maharashtra, India • Posted June 06, 2026

Job Type: Full-time
Location: Mumbai, Maharashtra
Posted: June 06, 2026
Category: Computer Occupations
Application Deadline: July 16, 2026

Role Description

About Lattice
At Lattice, we believe in building technology with focus and intent.
We develop

low-power programmable solutions

that enable innovation across edge AI, connectivity, and security. Our teams work across silicon, software, and systems—with a strong emphasis on

ownership, speed, and real impact .
Here, engineers don't just contribute to parts of a system—they help define

how the system works end-to-end , including the tools that bring silicon to life.

We're looking for a

Principal RTL Engineer

to lead the architecture and development of

FPGA debug infrastructure

within Lattice's tool ecosystem.
This is a unique opportunity to work on

on-chip debug, observability, and instrumentation capabilities , shaping how engineers analyze and optimize designs on Lattice platforms.
You'll operate at the intersection of

RTL, FPGA architecture, and tooling , with the ability to...

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