Principal Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.



+ Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment

+ Involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of the overall system-level solution.

+ Defining verification strategy from IP to top digital integration

+ Define requirements for block level and full-chip level verification infrastructure

+ Create test plans for unit-level and chip-level verification and post-silicon validation

+ Debug failures and drive in-time resolution of bugs

+ Create coverage monitors and drive coverage to required quality targets

+ Develop tools, test benches, and test suites (UVM, C++/C ) to execute test plans.

+ Write functional coverage, analyze both code and functional...