Remote Hardware Verification Engineer (SystemVerilog/UVM)
bogotá, distrito capital, rap (especial) central, Colombia • Posted June 08, 2026
Job Type:
Full-time
Location:
bogotá, distrito capital, rap (especial) central
Posted:
June 08, 2026
Category:
Ingeniería de calidad
Application Deadline:
July 18, 2026
Role Description
BairesDev is seeking a Hardware Verification Engineer in Colombia. This remote position focuses on verifying digital chip designs to ensure they meet technical specifications before fabrication. Responsibilities include developing verification strategies, optimizing testbenches using SystemVerilog, and defining coverage models. Ideal candidates will have 4+ years of verification experience and expertise in SystemVerilog and UVM. Join a multicultural team where you can collaborate globally and enjoy flexible hours and competitive compensation.
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