RTL Design Verification Engineer

Hi All,

Tech Mahindra hiring DFT Engineers and RTL (ASIC and FPGA) Engineers.

DFT Engineers

Exp:6-12yrs

NP: Immediate to 30days

RTL Engineers

Exp: 8-12yrs.

NP: Immediate to 30days

Job Description for DFT Engineer

Required Skills:

• 5-12 years of experience
• Experience in Scan insertion with compression for Stuck-At and At-Speed test.
• Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug
• Experience in MBIST insertion, simulation and debug on RTL and gates netlist
• Experience in Boundary Scan insertion, simulation and verification.
• Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)
• Good written and verbal communication skills in English
• STA DFT Test mode timing constraint development and analy...