Semiconductor Layout Engineering Lead

LTTS is hiring for Physical Design Lead with 7+ years of experience on below JD ::

JD for PnR – 7+ ’ experience

- IP/Block level PnR activities from Netlist to GDS-II.

- Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV.

- Knowledge of industry stanrd E tools (Synops, Cadence, Mentor)

- Worked on DSM technologies, tsmc 5nm and below experience preferred.

- Knowledge of scripting skills.

- Minimum Experience : 5+