Semiconductor Layout & Integration Leader

Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience.

Deatiled JD is below as mentioned...

Candidates with PnR – 8+ ’ experience

- IP/Block level PnR activities from Netlist to GDS-II.

- Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV.

- Knowledge of industry stanrd E tools (Synops, Cadence, Mentor)

- Worked on DSM technologies, tsmc 5nm and below experience preferred.

- Knowledge of scripting skills.

- Minimum Experience : 8+