Senior DDR Memory Validation Engineer (Post-Silicon)

A technology solutions provider in Penang, Malaysia, seeks a Senior Electrical Test and Debug Engineer. In this role, you will develop test plans, execute feature enablement, and debug electrical issues in new processors' memory subsystems. Ideal candidates will have a strong technical background in DDR interfaces and experience in developing platform-level test plans. Strong communication and multitasking abilities are essential. The role involves interaction with silicon design and requires familiarity with various testing and debugging tools.
#J-18808-Ljbffr