Senior Digital ASIC Design Engineer
Delft, South Holland, Netherlands • Posted May 26, 2026
Job Type:
Permanent
Location:
Delft, South Holland
Posted:
May 26, 2026
Category:
Computer Occupations
Application Deadline:
July 05, 2026
Role Description
Position: Senior Digital ASIC Design Engineer
Location: Delft, Amsterdam
About the company:
A start-up company on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. The vision is to revolutionize radio chip technology.
The team is currently built of 30 individuals, scaling to 40 in the next year.
This isn’t just about a job, it's about embracing high standards and boldly navigating unexpected challenges.
Key responsibilities:
•You will be responsible for the simulation and verification of digital block implemented in RTL for various functions including control state machine digital signal processing (DSP), and multiple clock domain interface management
•Post-layout simulation of complex mixed-signal SOC
•You will develop test benches and test cases for block-level functional verification
•Work with backend/implementation teams to address synthesis, timing,...
Location: Delft, Amsterdam
About the company:
A start-up company on a mission to conquer the high-power consumption challenges in Global Navigation Satellite Systems and IoT sensors. The vision is to revolutionize radio chip technology.
The team is currently built of 30 individuals, scaling to 40 in the next year.
This isn’t just about a job, it's about embracing high standards and boldly navigating unexpected challenges.
Key responsibilities:
•You will be responsible for the simulation and verification of digital block implemented in RTL for various functions including control state machine digital signal processing (DSP), and multiple clock domain interface management
•Post-layout simulation of complex mixed-signal SOC
•You will develop test benches and test cases for block-level functional verification
•Work with backend/implementation teams to address synthesis, timing,...
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