Senior Engineer I – Verification

Chennai, Tamil Nadu, India • Posted May 31, 2026

Job Type: Full time

Location: Chennai, Tamil Nadu

Posted: May 31, 2026

Category: Engineers

Application Deadline: July 10, 2026

Role Description

Job Summary
We are seeking a highly skilled Senior Engineer I – Verification with a strong understanding of full-chip verification and exposure to AMS (Analog/Mixed-Signal) environments. This role focuses on ensuring functional correctness and quality of complex SoC designs by developing and executing robust verification strategies across digital and mixed-signal domains.
Key Responsibilities
Lead and contribute to full-chip verification for complex SoC and mixed-signal designs
Develop and execute verification plans, testbenches, and methodologies using SystemVerilog and UVM
Collaborate with AMS, digital design, and architecture teams to validate mixed-signal behavior
Integrate and verify analog IP interactions within full-chip and subsystem environments
Drive coverage closure (functional, code, and assertions) at block, subsystem, and full-chip levels
Debug and resolve complex failures involving digital, anal...
                

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