Senior Formal Verification Engineer – AI SoC Development
Austin, TX, United States • Posted June 10, 2026
Job Type:
Full-time
Location:
Austin, TX
Posted:
June 10, 2026
Category:
other-general
Application Deadline:
June 18, 2026
Role Description
**Job Details:**
**Job Description:**
Intel’s AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs.
Key Responsibilities
+ Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
+ Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
+ Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
+ Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
+ Drive formal sign-off, including convergence analy...
**Job Description:**
Intel’s AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs.
Key Responsibilities
+ Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
+ Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
+ Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
+ Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
+ Drive formal sign-off, including convergence analy...
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