Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

Austin, TX, United States • Posted June 14, 2026

Job Type: Full-time
Location: Austin, TX
Posted: June 14, 2026
Category: other-general
Application Deadline: June 22, 2026

Role Description

**Job Details:**

**Job Description:**

**About the Role**

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.

In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.

**What You’ll Do**

**Key responsibilities will include but not limited to:**

+ Developing layout design methodology for testchip development in next generation process nodes
+ Working closely with Process Integration, Yield and QnR to ...

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