Senior Verification Engineer — SystemVerilog/UVM, Barcelona

A leading technology firm in Barcelona is looking for a Mid/Senior Verification Engineer. The role involves ensuring the correctness of complex digital designs within the Verification Team using advanced methodologies. Candidates should have a Master or PhD, 8+ years of industrial experience, and proficiency in SystemVerilog and UVM. Flexible schedules, competitive pay, and a supportive learning environment are part of the offer. Join us and enjoy some unique perks, including free Spanish lessons.
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