Senior Verification Engineer - SystemVerilog/UVM, SerDes

toronto, on, Canada • Posted June 01, 2026

Job Type: Full-time

Location: toronto, on

Posted: June 01, 2026

Category: Other-General

Application Deadline: July 11, 2026

Role Description

                    A leading company in digital technology is seeking a Senior Design Verification Engineer to enhance high-performance data communication systems. The role involves reviewing design specifications, leading verification tasks, and collaborating with cross-functional teams. Candidates should have strong skills in SystemVerilog and UVM, with a focus on advanced semiconductor projects in a supportive work culture.
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