SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ, United States • Posted June 05, 2026
Job Type:
Full-time
Location:
Phoenix, AZ
Posted:
June 05, 2026
Category:
other-general
Application Deadline:
June 11, 2026
Role Description
**Job Details:**
**Job Description:**
As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.
Key Responsibilities:
+ Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
+ Generate and verify timing constraints while addressing timing violations at...
**Job Description:**
As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.
Key Responsibilities:
+ Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
+ Generate and verify timing constraints while addressing timing violations at...
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