Sr. DDR PHY Design Engineer - Munich, Germany
bayern, germany, Bavaria, Germany • Posted June 07, 2026
Job Type:
Permanent
Location:
bayern, germany, Bavaria
Posted:
June 07, 2026
Category:
Engineers
Application Deadline:
July 17, 2026
Role Description
Job Summary:
In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and PD design teams, with a critical impact on delivering best in class phy designs. You will be required to do designs of best in class PHY design.
Description:
Core Responsibilities:
As a DDR PHY Design engineer you will be involved with all phases of phy design of high performance ddr interface from architecture, RTL to delivery of our final GDSII.
Your responsibilities include but are not limited to:
1.Participate in the architecture of next generation DDR PHY.
2.Design DDR PHY from architecture to micro-architecture.
3.RTL implementation of the micro-architecture.
4.Participate in clearly defining specification, testing and verification of the DDR PHY design.
5.Work closely with CAD, PD teams to implement RTL design into GDS.
6.Run various design verification flow at phy level and provide guidelin...
In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and PD design teams, with a critical impact on delivering best in class phy designs. You will be required to do designs of best in class PHY design.
Description:
Core Responsibilities:
As a DDR PHY Design engineer you will be involved with all phases of phy design of high performance ddr interface from architecture, RTL to delivery of our final GDSII.
Your responsibilities include but are not limited to:
1.Participate in the architecture of next generation DDR PHY.
2.Design DDR PHY from architecture to micro-architecture.
3.RTL implementation of the micro-architecture.
4.Participate in clearly defining specification, testing and verification of the DDR PHY design.
5.Work closely with CAD, PD teams to implement RTL design into GDS.
6.Run various design verification flow at phy level and provide guidelin...
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