Sr Principal Design Engineer

Sector 8, Uttar Pradesh, India • Posted June 26, 2026

Job Type: Full-time

Location: Sector 8, Uttar Pradesh

Posted: June 26, 2026

Category: Engineers

Application Deadline: August 05, 2026

Role Description

Description
 :RTL Design Engineer for DDR Memory Controller IP development team.
The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements:
BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
RTL Design using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
AXI3/4 experience is d...
                

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