Sr. Principal Functional Verification Engineer: Applied ML

Belo Horizonte, Brazil, Brazil • Posted June 05, 2026

Job Type: Full-time
Location: Belo Horizonte, Brazil
Posted: June 05, 2026
Category: other-general
Application Deadline: June 11, 2026

Role Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. (http://www.cadence.com/) is looking for a motivated Sr. Principal Functional Verification Engineer: Applied ML to be part of the ChipStack AI Super Agent (https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2026/cadence-unleashes-chipstack-ai-super-agent-pioneering-a-new.html) team in Belo Horizonte - working on the world’s first agentic AI platform that autonomously designs and verifies chips with up to 10× productivity gains. We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI t...

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