Sr Principal Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Qualifications

Minimal qualification requires BS/MS degree EE or CS with of experience in relevant experience.

As a you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM (LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products.

·Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support.

·Must analyze product-wide feature requirements and execute on their verification.

·Must integrate additional related tools and processes—including coverage, reporting, and regressing—to build a robust team-level verification ...