Staff/ Sr Staff Engineer, Physical Design

noida, uttar pradesh, India • Posted June 09, 2026

Job Type: Full-time

Location: noida, uttar pradesh

Posted: June 09, 2026

Category: Other-General

Application Deadline: July 19, 2026

Role Description

Job Description
Experience:  7-10 years 
Role Summary  
We are seeking an experienced Physical Design Engineer  with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams. 
Key Responsibilities  
Own RTL synthesis from elaboration to final sign‑off. 
Develop and debug design constraints and support DFT insertion. 
Understand Physical design cycle and different handshaking across teams. 
Perform and close logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists. 
Create, maintain, and debug UPF, ensuring alignment with FE power intent. 
Define and manage power domains (power switches, isolation, retention, always‑on). 
Support low‑power sign‑off (V...
                

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