Technical Lead Manager, Machine Learning, Memory Subsystem Design

Sunnyvale, CA, United States • Posted June 03, 2026

Job Type: Full-time
Location: Sunnyvale, CA
Posted: June 03, 2026
Category: other-general
Application Deadline: June 08, 2026

Role Description

Technical Lead Manager, Machine Learning, Memory Subsystem Design

_corporate_fare_ Google _place_ Sunnyvale, CA, USA

**Advanced**

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
+ 15 years of experience in semiconductor design or design verification.
+ 6 years of experience in people management, developing employees.
+ Experience in designing or verifying DRAM-based memory subsystems.

**Preferred qualifications:**

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience in creating and validating HBM-based memory subsystems.

**About the job**

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